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  • The contest is supported by CEDA (IEEE Council on Electronic Design Automation). The top teams in the contest will receive cash awards sponsored by CEDA

  • The contest will be administrated by Luis Guerra e Silva, L. Miguel Silveira and José Monteiro from INESC-ID, and Kerim Kalafala from IBM. Please send all emails regarding to the contest to patmos-tac@algos.inesc-id.pt (adding [PATMOS-TAC] to your subject line for any emails regarding the contest).

  • To be considered for the contest, you must register by May 31 June 15, 2011, on the contest web site: http://patmos-tac.inesc-id.pt This will enable the administrators to create a targeted mailing list to email relevant contest information.

  • Important Dates:
    • June 7: Finalized rules and evaluation metrics.
    • May 31 June 15 (EXTENDED): Deadline for registering for the contest.
    • June 31 July 15 (EXTENDED): Submission of alpha binary to ensure compatibility.
    • Aug 16 August 21 (EXTENDED): Final binary due from each team.
    • Aug 26: Announcement of winners.

  • Problem: the participants will be asked to submit the binaries for a static timing analysis tool. The detailed information about required functionality and binary architecture will be released very soon. Basic timing quantities such as delay, slew, arrival times, etc will be computed for a set of circuits. A simple delay model will be used and netlist and output formats will be defined at a later stage.

  • Benchmarks: we will use 15 to 20 benchmark circuits (the value may vary at the end) to evaluate the tool from each team. Some of the benchmarks will be released so the contestants can test their codes, while others will be reserved for evaluation purposes. The full set of benchmarks will be released to the public after the contest.

  • Machines: the contest machine will be installed with Linux system and gcc. The detailed information will be released later for the versions of gcc, linux cpu speed/memory configuration, as well as the number of cores available.

  • Metrics: the evaluation metrics will be based on three factors: correctness of timing estimates, CPU time and memory.